Conventionally, in a semiconductor integrated circuit, a high performance and a small chip area are realized by designing a dedicated LSI (Large Scale Integrated Circuit), and a low manufacturing cost is realized by mass production. However, the development is required for each individual application, and there is a tendency to increase the development cost. Additionally, it is not easy to change a function of a dedicated LSI. In general, when it is required to change the function, it is required to reconstruct part of or a whole of the design and the manufacturing process.
When the function in a FPGA (field programmable gate array) is changed, it is not necessary to re-execute the manufacturing process but it is necessary to re-execute the designing process after the RTL (Register Transfer Level) design. In particular, in the timing design, the length of a wiring channel for connecting between logic elements is unknown until the logic elements are laid out. In general, since a roundabout amount of the wiring channel path is large, the FPGA has a low operating frequency than the dedicated LSI and ASIC (Application Specific Integrated Circuit). Thus, there is a problem that the maximum operating frequency of the FPGA may vary every time when the FPGA is re-designed. Further, since a large channel region is necessary to connect between logic elements, a chip area of the FPGA is a few times or ten times as large as that of the dedicated LSI, and therefore, the cost reduction of the FPGA is difficult.
Software processes by a processor or a DSP (Digital Signal Processor) are flexible to the function change and have a high general versatility, so that mass production and low cost are generally possible. However, the software processes are generally bad with a bit-by-bit basis operation as compared with a product-sum operation and a register-by-register basis logical operation. Additionally, in complicated communication processing or advanced image processing, the software processes cannot provide sufficient performance as compared with a dedicated LSI. A typical approach for enhancing the performance is an increase in operating frequency. However, this poses a problem of increasing power consumption.
A DRP (Dynamic Reconfigurable Processor) is capable of coping with the function change and is expected to perform high speed processing, as compared with software processing by a typical processor. However, the number of logic reconfiguration elements in an existing product is about from 16 to 1024 and smaller than in FIPGA. This poses a flexibility problem. Additionally, some DRPs require a relatively large wiring channel region for connecting between the logic reconfiguration elements. In some cases, a large roundabout amount of the wiring for connecting with this wiring channel is required. Thus, a signal transmission delay being a critical path is large. The increase in the operating frequency is difficult as compared with a dedicated LSI. Moreover, a wiring channel region for connecting a logic reconfiguration element to a memory for the logic reconfiguration element is required. Thus, because of a large area, the cost reduction is difficult as compared with a dedicated LSI and an ASIC.